From 230dbd6d3c194d9f839d31a0a579ef99befdd097 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 28 Jan 2021 23:40:52 +0100
Subject: soc/amd/cezanne: add empty ramstage FCH support

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/cezanne/fch.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 src/soc/amd/cezanne/fch.c

(limited to 'src/soc/amd/cezanne/fch.c')

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
new file mode 100644
index 0000000000..f853ecee93
--- /dev/null
+++ b/src/soc/amd/cezanne/fch.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/southbridge.h>
+
+void fch_init(void *chip_info)
+{
+}
+
+void fch_final(void *chip_info)
+{
+}
-- 
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