From 8c178910221ea59936dd31644bde68a66d586dce Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 7 Sep 2023 16:01:22 +0200 Subject: soc/amd/cezanne,common: expose eMMC device in ACPI when enabled When the eMMC MMIO device is enabled in the devicetree, it needs to be exposed in ACPI in order for the OS driver to be able to attach to it. The Cezanne eMMC controller isn't used in google/guybrush, so this the code path where the eMMC MMIO device is enabled in the devicetree can't be easily tested. Signed-off-by: Felix Held Change-Id: I69ff79b2d1c6a08cf333a2bb3996931962c2c102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77989 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/amd/cezanne/acpi/mmio.asl | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'src/soc/amd/cezanne/acpi') diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl index 930ca169d3..c138cbcb03 100644 --- a/src/soc/amd/cezanne/acpi/mmio.asl +++ b/src/soc/amd/cezanne/acpi/mmio.asl @@ -58,6 +58,42 @@ Device (GPIO) } } +Device (MMC0) +{ + Name (_HID, "AMDI0040") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IMMC + } Else { + IRQN = PMMC + } + If (IRQN == 0x1f) { + Return (ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } +} + Device (FUR0) { Name (_HID, "AMDI0020") -- cgit v1.2.3