From 0b123dd72e82eaa90b3682cd13b57a88e634c53e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 12 Feb 2021 15:13:57 -0700 Subject: soc/amd/cezanne/acpi: Add pci0.asl This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/acpi/soc.asl | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/cezanne/acpi/soc.asl') diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index 1a45b0ae8a..c935dc3eea 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -9,6 +9,8 @@ Scope(\_SB) { #include "pci_int_defs.asl" #include "mmio.asl" + + #include "pci0.asl" } /* End \_SB scope */ #include -- cgit v1.2.3