From ea32c52a0eb9eb9f8cb9ef886e2120d1d5f35753 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 13 Feb 2021 01:42:44 +0100 Subject: soc/amd/cezanne: add partial data fabric setup I'm not 100% sure yet if this code will be common for all AMD SoCs, so I'll add a copy for Cezanne for now. This part of the code should probably be reworked after the initial bringup of Cezanne anyway. DF MMIO register configuration at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 a0 0 0 4 a3 fed0 fed0 5 a0 0 0 6 a0 0 0 7 a0 0 0 DF MMIO register configuration at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 10a3 fed0 fedf 4 a0 0 0 5 a0 0 0 6 a0 0 0 7 a0 0 0 Signed-off-by: Felix Held Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/cezanne/Makefile.inc') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d395089242..697d412464 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c -- cgit v1.2.3