From 65783fbeb4d2b8180165b36083023f94bdccbdb7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 4 Dec 2020 17:38:46 +0100 Subject: soc/amd/cezanne: use common TSC and monotonic timer code Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/amd/cezanne/Makefile.inc') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d1d8e97099..d4f585fed8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -7,7 +7,6 @@ bootblock-y += bootblock.c romstage-y += romstage.c ramstage-y += chip.c -ramstage-y += timer.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include -- cgit v1.2.3