From 230dbd6d3c194d9f839d31a0a579ef99befdd097 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 28 Jan 2021 23:40:52 +0100 Subject: soc/amd/cezanne: add empty ramstage FCH support Signed-off-by: Felix Held Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/cezanne/Makefile.inc') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index bcf1d722c4..9422a4db31 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += romstage.c romstage-y += uart.c ramstage-y += chip.c +ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += reset.c -- cgit v1.2.3