From 0ffebacfd798279279eae56ce04989735ce4862b Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 5 Feb 2021 22:26:00 +0100
Subject: soc/amd/cezanne/pcie_gpp: scan internal PCI buses

TEST=The devices on the internal buses now get resources assigned.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/cezanne/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/amd/cezanne/Makefile.inc')

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 9422a4db31..45e98a5e48 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -28,6 +28,7 @@ ramstage-y	+= chip.c
 ramstage-y	+= fch.c
 ramstage-y      += fsp_params.c
 ramstage-y	+= gpio.c
+ramstage-y	+= pcie_gpp.c
 ramstage-y      += reset.c
 ramstage-y	+= uart.c
 
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