From 4be064a1d8b3693954c637e578cf3d6aec625105 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 8 Dec 2020 17:21:04 +0100 Subject: soc/amd/cezanne: add common SMBus code to build Since the IOAPIC in the FCH gets set up in the SMBus code, also select IOAPIC in Kconfig. Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/cezanne/Kconfig') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index fe248c6097..be45de4145 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,11 +13,13 @@ config SOC_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H config EARLY_RESERVED_DRAM_BASE -- cgit v1.2.3