From 31f7a726ff6aba214f32c10878075ba161bbe97c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 23 Mar 2021 14:53:58 -0600 Subject: soc/amd/cezanne: save chipset state to CBMEM Guybrush complains that this is missing during the boot, so add it to cezanne. I verified that the registers in gpio.c are correct. BUG=b:184549804 TEST=Build and boot Signed-off-by: Martin Roth Signed-off-by: Felix Held Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/cezanne/Kconfig') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a27b26d124..7a1146f779 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PM + select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI -- cgit v1.2.3