From 28d040840998aa616b403fb9325238374d3730b8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 00:47:45 +0200 Subject: sec/intel/txt/common.c: Only log ACM error on failure The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is set, or if CBnT is supported and bit 61 is set. Moreover, this is only applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers). This allows TXT to work on client platforms, where these registers are regular scratchpads and are not necessarily written to by the BIOS ACM. Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/security/intel/txt/common.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/security') diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 5f8a976946..737ab0a4be 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -303,8 +303,6 @@ int intel_txt_run_bios_acm(const u8 input_params) intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); return -1; } - if (intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)) != 1) - return -1; return 0; } -- cgit v1.2.3