From dcae8074bf7f575a267b4253b1242e5cbc9565c7 Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Wed, 29 Jul 2020 14:22:41 -0700 Subject: drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate. A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register. BUG=b:154333137 TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Signed-off-by: Jes Bodi Klinke Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da Reviewed-on: https://review.coreboot.org/c/coreboot/+/43741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner --- src/security/tpm/tss/vendor/cr50/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/security/tpm/tss') diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index f606459d65..52c73859d8 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -12,4 +12,11 @@ config POWER_OFF_ON_CR50_UPDATE help Power off machine while waiting for CR50 update to take effect. +config CR50_USE_LONG_INTERRUPT_PULSES + bool + default n + help + Whether to request longer interrupt pulses using Cr50 BOARD_CFG register. + If the Cr50 firmware is too old, it will not be able to honor the request. + endif -- cgit v1.2.3