From 463e44bedbf3d5f24b8e6e19475b5155b523309a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 5 Oct 2020 13:58:16 +0200 Subject: security/intel/txt: Add and use DPR register layout This simplifies operations with this register's bitfields, and can also be used by TXT-enabled platforms on the register in PCI config space. Change-Id: I10a26bc8f4457158dd09e91d666fb29ad16a2087 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46050 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/security/intel/txt/txt_register.h | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'src/security/intel/txt/txt_register.h') diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index bd546b5825..bbf0a7e72d 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -91,15 +91,6 @@ #define TXT_BIOSACM_ERRORCODE (TXT_BASE + 0x328) #define TXT_DPR (TXT_BASE + 0x330) -#define TXT_DPR_LOCK_SHIFT 0 -#define TXT_DPR_LOCK_SIZE_SHIFT 4 -#define TXT_DPR_LOCK_SIZE_MASK 0xff -#define TXT_DPR_TOP_ADDR_SHIFT 20 -#define TXT_DPR_TOP_ADDR_MASK 0xfff - -#define TXT_DPR_LOCK_MASK (1 << TXT_DPR_LOCK_SHIFT) -#define TXT_DPR_LOCK_SIZE(x) ((x) << TXT_DPR_LOCK_SIZE_SHIFT) -#define TXT_DPR_TOP_ADDR(x) ((x) << TXT_DPR_TOP_ADDR_SHIFT) #define TXT_ACM_KEY_HASH (TXT_BASE + 0x400) #define TXT_ACM_KEY_HASH_LEN 0x4 @@ -160,6 +151,20 @@ /* MSRs */ #define IA32_MCG_STATUS 0x17a +/* DPR register layout, either in PCI config space or TXT MMIO space */ +union dpr_register { + struct { + uint32_t lock : 1; /* [ 0.. 0] */ + uint32_t prs : 1; /* [ 1.. 1] and only present on PCI config */ + uint32_t epm : 1; /* [ 2.. 2] and only present on PCI config */ + uint32_t : 1; + uint32_t size : 8; /* [11.. 4] */ + uint32_t : 8; + uint32_t top : 12; /* [31..20] */ + }; + uint32_t raw; +}; + typedef enum { CHIPSET_ACM = 2, } acm_module_type; -- cgit v1.2.3