From f5a57a883b6586c0e6dce9e6e34add09a96e647e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 8 Jan 2019 22:15:53 +0100 Subject: mb: Move timestamp_add_now to northbridge x4x Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/x4x/raminit.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index b3b84d8061..d9fa49d9da 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "iomap.h" #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include /* smbus_read_byte */ @@ -34,6 +35,7 @@ #include #include #include +#include #define MRC_CACHE_VERSION 0 @@ -639,6 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) int fast_boot, cbmem_was_inited, cache_not_found; struct region_device rdev; + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); @@ -728,4 +731,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) outb(0x6, 0xcf9); halt(); } + + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); } -- cgit v1.2.3