From e80ce0a134bc88581db40b02ce250bee5adba3a3 Mon Sep 17 00:00:00 2001 From: Xavi Drudis Ferran Date: Mon, 28 Feb 2011 03:12:00 +0000 Subject: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step for my CPU (rev C3) mentioned in BKDG 2.4.2.6 (5) that was missing Signed-off-by: Xavi Drudis Ferran Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdht/AsPsDefs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 07f46631b2..13e6548873 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -153,6 +153,8 @@ #define PS_2 0x00020000 /* P-state 2 */ #define PS_CPU_DID_1 0x40 /* Cpu Did 1 */ +#define NB_VID1_MASK 0x00003f80 /* F3x1F4[NbVid1]*/ +#define NB_VID1_SHIFT 7 /* F3x1F4[NbVid1] */ -- cgit v1.2.3