From e1e11e63afab8e461ac7e6466c9a7f9f47a10702 Mon Sep 17 00:00:00 2001 From: York Yang Date: Mon, 5 Jan 2015 10:04:45 -0700 Subject: intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/8107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++ src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++ 2 files changed, 17 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 80a22bf1ea..d3828c7764 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087f85..3f8690a388 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -143,6 +144,12 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) break; } } + + /* Set PCIe de-emphasis */ + UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); + UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); } /* Set up the Rangeley specific structures for the call into the FSP */ -- cgit v1.2.3