From e07df9d78351cda0818309fc7f3e78d8057d421e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 9 Apr 2018 22:03:21 +0200 Subject: nb/intel/i945: Enable and allocate 8M for TSEG TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/early_init.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index bf486a0aaf..7de2c73fc9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -192,6 +192,11 @@ static void i945_setup_bars(void) gfxsize = 2; pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); -- cgit v1.2.3