From ddc88286979ebce24320f1fc44ba881ea8fdf114 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 27 Feb 2017 16:27:21 +0100 Subject: nb/x4x/raminit.c: Remove ME locking code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code ought not to run if ME is disabled. It also prohibits writing to some GMCH regs like GGC bit1. Intel ® 4 Series Chipset Family datasheet refers to this as "ME stolen Memory lock" without actually describing this functionality. Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/18513 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/x4x/raminit_ddr2.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index eca7189145..35caaa6b73 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -2106,15 +2106,19 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - if (RANK_IS_POPULATED(s->dimms, 0, 0) - || RANK_IS_POPULATED(s->dimms, 1, 0)) { - MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + /* + * FIXME: This locks some registers like bit1 of GGC + * and is only needed in case of ME being used. + */ + if (ME_UMA_SIZEMB != 0) { + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); } - if (RANK_IS_POPULATED(s->dimms, 0, 1) - || RANK_IS_POPULATED(s->dimms, 1, 1)) { - MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); - } - MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); } -- cgit v1.2.3