From dd4a6d2357decf0cf505370234b378985c68f97f Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 27 Feb 2013 22:50:12 -0600 Subject: coreboot: dynamic cbmem requirement Dynamic cbmem is now a requirement for relocatable ramstage. This patch replaces the reserve_* fields in the romstage_handoff structure by using the dynamic cbmem library. The haswell code is not moved over in this commit, but it should be safe because there is a hard requirement for DYNAMIC_CBMEM when using a reloctable ramstage. Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/haswell/northbridge.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 87081385b5..53c2f366c2 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -543,21 +543,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -#if CONFIG_EARLY_CBMEM_INIT -int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size) -{ - uint32_t tseg; - - /* Put the CBMEM location just below TSEG. */ - *tables_size = HIGH_MEMORY_SIZE; - tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), - TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE; - *tables_base = tseg; - - return 0; -} -#endif - static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME -- cgit v1.2.3