From da43737c4ee04c282bbb31a42f21a094060dcc07 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 24 Jan 2021 18:34:51 +0100 Subject: nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide. Clamp any values that would overflow this field. Bits in TC_DTP already get set when the tXP and/or tXPDLL values are large. Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6f02998433..d6a8aa550a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -170,15 +170,16 @@ void dram_timing_regs(ramctr_timing *ctrl) /* Other parameters */ const union tc_othp_reg tc_othp = { - .tXPDLL = ctrl->tXPDLL, - .tXP = ctrl->tXP, + .tXPDLL = MIN(ctrl->tXPDLL, 31), + .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, .tCPDED = 2, .tPRPDEN = 1, }; /* - * If tXP and tXPDLL are very high, we need to increase them by one. + * If tXP and tXPDLL are very high, they no longer fit in the bitfields + * of the TC_OTHP register. If so, we set bits in TC_DTP to compensate. * This can only happen on Ivy Bridge, and when overclocking the RAM. */ const union tc_dtp_reg tc_dtp = { -- cgit v1.2.3