From c4d1b47ad95f479981de9a30b5906c81dd720377 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 31 Jan 2021 08:26:01 +0100 Subject: nb/intel/gm45/bootblock.c: include Also rename 'reg' to 'reg32'. Change-Id: Id741f636162a8a228bca069637993422deb5e09c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/gm45/bootblock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 9c45f7e3f8..e2cabdb166 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include #include #include "gm45.h" @@ -31,7 +31,7 @@ void bootblock_early_northbridge_init(void) * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } -- cgit v1.2.3