From c2d6f5f4da3c89b3f432f05fb31879b8d4d50698 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 23:48:51 +0100 Subject: nb/intel/ironlake: Add comment about MCH scan chains Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/raminit.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index ecf8ef8576..beb22445fe 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -101,6 +101,15 @@ static void read128(u32 addr, u64 * out) out[1] = ret.hi; } +/* + * Ironlake memory I/O timings are located in scan chains, accessible + * through MCHBAR register groups. Each channel has a scan chain, and + * there's a global scan chain too. Each chain is broken into smaller + * sections of N bits, where N <= 32. Each section allows reading and + * writing a certain parameter. Each section contains N - 2 data bits + * and two additional bits: a Mask bit, and a Halt bit. + */ + /* OK */ static void write_1d0(u32 val, u16 addr, int bits, int flag) { -- cgit v1.2.3