From b7341da19133991efd29880849bdaab29a6e243d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Dec 2023 14:53:45 +0100 Subject: nb/intel/sandybridge/raminit: Add tCPDED corner case tCPDED is always 1, except for steppings earlier than Sandy Bridge D0. Reduces the differences to MRC.bin. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/northbridge/intel/sandybridge/raminit_common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index fea3ca4e8f..51d6786f34 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -171,7 +171,7 @@ void dram_timing_regs(ramctr_timing *ctrl) .tXPDLL = MIN(ctrl->tXPDLL, 31), .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, - .tCPDED = 2, + .tCPDED = 1, .tPRPDEN = 1, }; @@ -2816,7 +2816,10 @@ void final_registers(ramctr_timing *ctrl) union tc_othp_reg tc_othp = { .raw = mchbar_read32(TC_OTHP_ch(channel)), }; - tc_othp.tCPDED = 1; + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) < SNB_STEP_D0) + tc_othp.tCPDED = 2; + else + tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); /* 64 DCLKs until idle, decision per rank */ -- cgit v1.2.3