From b33c6fbfd5f9050686b97f2fe3e4b94862a96a74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 17 Feb 2021 20:43:04 +0200 Subject: nb/intel/x4x,sandybridge: Move INITRAM timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's not have CBMEM hooks in between the different INITRAM timestamps. Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit.c | 7 ++++--- src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/romstage.c | 3 --- src/northbridge/intel/x4x/raminit.c | 3 ++- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 93a2eae9c6..0dcd952595 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -298,6 +298,8 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) size_t mrc_size; ramctr_timing *ctrl_cached = NULL; + timestamp_add_now(TS_BEFORE_INITRAM); + MCHBAR32(SAPMCTL) |= 1; /* Wait for ME to be ready */ @@ -458,6 +460,8 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) report_memory_config(); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); @@ -473,8 +477,5 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) void perform_raminit(int s3resume) { post_code(0x3a); - - timestamp_add_now(TS_BEFORE_INITRAM); - init_dram_ddr3(s3resume, cpu_get_cpuid()); } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 8d13e55699..149860de05 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -361,6 +361,7 @@ void perform_raminit(int s3resume) pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + timestamp_add_now(TS_AFTER_INITRAM); /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index fad8e2f91a..49f334e397 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include "sandybridge.h" #include #include @@ -63,8 +62,6 @@ void mainboard_romstage_entry(void) perform_raminit(s3resume); - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_reset_pmcon(); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 586df389a8..59abe4d1de 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -684,6 +684,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) pci_or_config8(HOST_BRIDGE, 0xf4, 1); + timestamp_add_now(TS_AFTER_INITRAM); + printk(BIOS_DEBUG, "RAM initialization finished.\n"); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); @@ -695,6 +697,5 @@ void sdram_initialize(int boot_path, const u8 *spd_map) system_reset(); } - timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n"); } -- cgit v1.2.3