From a8753e9cbbfc38516b68eab14b806c441c6276b9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Apr 2021 14:34:37 +0200 Subject: haswell/broadwell: Replace remaining MCHBAR accessors Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 5f74a8973f..9660961c4e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -174,7 +174,7 @@ static void sdram_initialize(struct pei_data *pei_data) * Ensure the mc_init_done_ack bit is set before continuing. Otherwise, * attempting to access memory will lock up the system. */ - if (!(MCHBAR32(MC_INIT_STATE_G) & (1 << 5))) { + if (!(mchbar_read32(MC_INIT_STATE_G) & (1 << 5))) { printk(BIOS_EMERG, "Memory controller did not acknowledge raminit.\n"); die("MRC raminit failed\n"); } -- cgit v1.2.3