From 9cbf26d18e0263c964dd8faf7bc04d7dbb468337 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 31 Jan 2021 08:31:20 +0100 Subject: nb/intel/sandybridge/bootblock.c: include Also rename 'reg' to 'reg32'. Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/bootblock.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 529f4f886d..92f9aeee49 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include #include + #include "sandybridge.h" static uint32_t encode_pciexbar_length(void) @@ -28,7 +29,7 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } -- cgit v1.2.3