From 985821c4f2feda41ed2d1ab83f6ae7b8f15197bd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 5 Jan 2021 14:38:57 +0100 Subject: cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE". It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets should have at least 256K L2 cache. That is plenty for XIP RO cache of bootblock + romstage and a 32K CAR. Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- src/northbridge/intel/x4x/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8226fe90ee..00e9a3ad21 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select PARALLEL_MP select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES - select NO_CBFS_MCACHE config CBFS_SIZE hex -- cgit v1.2.3