From 8e646e74b3d5e1d4a5e8114f03046f3d7b6ad042 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 5 Jun 2018 11:19:22 +0200 Subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/northbridge/intel/haswell/Kconfig | 13 +++++++++---- src/northbridge/intel/haswell/Makefile.inc | 3 ++- src/northbridge/intel/haswell/bootblock.c | 11 +++++------ 3 files changed, 16 insertions(+), 11 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 082f2d63d9..242ab18c49 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,6 +22,8 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK +# select BOOTBLOCK_CONSOLE TODO: route LPC if NORTHBRIDGE_INTEL_HASWELL @@ -29,10 +31,6 @@ config VBOOT select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/haswell/bootblock.c" - config VGA_BIOS_ID string default "8086,0166" @@ -63,6 +61,13 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 055c2a8a0d..7abbccacd2 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -26,7 +28,6 @@ romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index e503e01fa1..2c1bd58dde 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -12,11 +12,10 @@ */ #include +#include +#include "haswell.h" -/* Just re-define this instead of including haswell.h. It blows up romcc. */ -#define PCIEXBAR 0x60 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; @@ -33,7 +32,7 @@ static void bootblock_northbridge_init(void) * 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); } -- cgit v1.2.3