From 8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 15 Feb 2013 21:45:06 -0600 Subject: haswell: add multipurpose SMM memory region The SMM region is available for multipurpose use before the SMM handler is relocated. Provide a configurable sized region in the TSEG for use before the SMM handler is relocated. This feature is implemented by making the reserved size a Kconfig option. Also make the IED region a Kconfig option as well. Lastly add some sanity checking on the Kconfig options. Change-Id: Idd7fccf925a8787146906ac766b7878845c75935 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2804 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/intel/haswell/haswell.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 3a1803858a..ba88722452 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -43,8 +43,8 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 +/* Intel Enhanced Debug region */ +#define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ -- cgit v1.2.3