From 8ad0a4c0b88718a0b0ba4ba934ff526fe6875702 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 7 Jun 2020 18:41:33 +0200 Subject: nb/intel/gm45/iommu.c: Fix regression when updating PCI command Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register) uses `pci_read_config8` to read the PCI command register, which does not correspond with what has been stated in the commit message. Moreover, it potentially breaks things, as the upper byte of the PCI command register is now being cleared. So, restore the original behaviour of the code, using 16-bit accesses. Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register) Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/northbridge/intel/gm45/iommu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 10e0d02066..439127d17d 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -43,9 +43,7 @@ void init_iommu() memset(bar, 0, 2<<20); /* and now disable again */ - u16 cmd = pci_read_config8(igd, PCI_COMMAND); - cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config16(igd, PCI_COMMAND, cmd); + pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); } -- cgit v1.2.3