From 7176a54c2b4c1a95219c5ab9e7b7b12a8ab6b0e2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 13 Dec 2019 17:08:49 +0100 Subject: Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 3 ++- src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl | 2 +- src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 3 ++- 6 files changed, 8 insertions(+), 6 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index fad157da29..06199a1b07 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ @@ -125,6 +125,7 @@ Device(PE23) { /* Northbridge function 3 */ Device(NBF3) { + Name(_ADR, 0x00180003) /* k10temp thermal zone */ #include "thermal_mixin.asl" diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 96c2d8bfac..9a1fa9ed88 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index a7e8307349..f74b31a080 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index de47bc2151..c2b3aac4c5 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 4a48aaf401..d54f985e90 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index b317ccf1ea..f74b31a080 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -16,9 +16,10 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + /* Describe the Northbridge devices */ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ -- cgit v1.2.3