From 6c2568f4f58b9a1b209c9af36d7f980fde784f08 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 25 Sep 2020 09:30:44 -0700 Subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/northbridge/intel/x4x/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8432..00e9a3ad21 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config CBFS_SIZE hex -- cgit v1.2.3