From 62b3513d63088ce7c0b324e2a6a88e31fec5a328 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 26 Aug 2009 18:14:30 +0000 Subject: Remove a couple of CONFIG_ prefixes that shouldn't have happened. Signed-off-by: Patrick Georgi Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdfam10/amdfam10_acpi.c | 8 ++++---- src/northbridge/ibm/cpc710/cpc710_pci.c | 4 ++-- src/northbridge/ibm/cpc710/cpc710_pci.h | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c index 77fd3ccb12..d0c9baf6fc 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c +++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c @@ -190,7 +190,7 @@ void update_ssdt(void *ssdt) u8 *CBST; u8 *CBBX; u8 *CBS2; - u8 *CONFIG_CBB2; + u8 *CBB2; int i; @@ -208,7 +208,7 @@ void update_ssdt(void *ssdt) HCDN = ssdt+0x57a; //+5 will be next HCDN CBBX = ssdt+0x61f; // CBST = ssdt+0x626; - CONFIG_CBB2 = ssdt+0x62d; // + CBB2 = ssdt+0x62d; // CBS2 = ssdt+0x634; for(i=0;i32)) { *CBS2 = 0x0f; - *CONFIG_CBB2 = (u8)(CONFIG_CBB-1); + *CBB2 = (u8)(CONFIG_CBB-1); } else { *CBS2 = 0x00; - *CONFIG_CBB2 = 0x00; + *CBB2 = 0x00; } } diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c index 2b6024e5b9..233e119baf 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.c +++ b/src/northbridge/ibm/cpc710/cpc710_pci.c @@ -45,7 +45,7 @@ cpc710_pci_init(void) setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE); setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE); setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE); - setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32CONFIG_IO_BASE); + setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE); setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000); setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080); setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000); @@ -94,7 +94,7 @@ cpc710_pci_init(void) setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE); setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE); setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE); - setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64CONFIG_IO_BASE); + setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE); setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000); setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080); diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h index 0b3374ebd4..a7f64dfcd8 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.h +++ b/src/northbridge/ibm/cpc710/cpc710_pci.h @@ -28,13 +28,13 @@ #define CPC710_PCI32_MEM_SIZE 0xf8000000 #define CPC710_PCI32_MEM_BASE 0xc0000000 #define CPC710_PCI32_IO_SIZE 0xf8000000 -#define CPC710_PCI32CONFIG_IO_BASE 0x80000000 +#define CPC710_PCI32_IO_BASE 0x80000000 //#define CPC710_PCI64_CONFIG 0xff400000 //#define CPC710_PCI64_MEM_SIZE 0xf8000000 //#define CPC710_PCI64_MEM_BASE 0xc8000000 //#define CPC710_PCI64_IO_SIZE 0xf8000000 -//#define CPC710_PCI64CONFIG_IO_BASE 0x88000000 +//#define CPC710_PCI64_IO_BASE 0x88000000 #define CPC710_PCIL0_PSEA 0xf6110 #define CPC710_PCIL0_PCIDG 0xf6120 -- cgit v1.2.3