From 5ee9bc18407e4c2cad8e1c9e222ca16051d4b9b4 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 31 Oct 2017 10:49:52 +0100 Subject: nb/intel/sandybridge/raminit: Set REFIx9 according to spec Set tREFIx9 to 8.9*tREFI/1024 as suggested in xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Use the minimum value of REFI*8.9 and tRASmax as suggested by 3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9. Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/22259 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/raminit_common.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b82075e58b..5cf9b69873 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -264,16 +264,18 @@ void dram_timing_regs(ramctr_timing *ctrl) dram_odt_stretch(ctrl, channel); - // REFI - reg = 0; - val32 = ctrl->tREFI; - reg = (reg & ~0xffff) | val32; - val32 = ctrl->tRFC; - reg = (reg & ~0x1ff0000) | (val32 << 16); - val32 = (u32) (ctrl->tREFI * 9) / 1024; - reg = (reg & ~0xfe000000) | (val32 << 25); - printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, - reg); + /* + * TC—Refresh timing parameters + * The tREFIx9 field should be programmed to minimum of + * 8.9*tREFI (to allow for possible delays from ZQ or + * isoc) and tRASmax (70us) divided by 1024. + */ + val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + + reg = ((ctrl->tREFI & 0xffff) << 0) | + ((ctrl->tRFC & 0x1ff) << 16) | + (((val32 / 1024) & 0x7f) << 25); + printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; MCHBAR32(0x400 * channel + 0x4294) |= 0xff; -- cgit v1.2.3