From 58a89537931cd243c6ddbb9ff435bc5862fc64b0 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 12 Jun 2018 22:58:19 +0200
Subject: Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common
 location"

In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/northbridge/intel/nehalem/early_init.c      | 1 -
 src/northbridge/intel/nehalem/nehalem.h         | 1 -
 src/northbridge/intel/nehalem/raminit.c         | 1 -
 src/northbridge/intel/sandybridge/early_init.c  | 1 -
 src/northbridge/intel/sandybridge/sandybridge.h | 1 -
 5 files changed, 5 deletions(-)

(limited to 'src/northbridge')

diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 1424b911e9..0a9b408dcc 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -25,7 +25,6 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <arch/cpu.h>
-#include <southbridge/intel/common/rcba.h>
 
 #include "nehalem.h"
 
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index bbdd290e8a..20c0bbc5e6 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -168,7 +168,6 @@ typedef struct {
 
 #define QUICKPATH_BUS 0xff
 
-#include <southbridge/intel/common/rcba.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 
 /* Everything below this line is ignored in the DSDT */
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 6a27b576e0..bd2042e418 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -56,7 +56,6 @@ typedef u32 device_t;
 
 #include "nehalem.h"
 
-#include <southbridge/intel/common/rcba.h>
 #include "southbridge/intel/ibexpeak/me.h"
 
 #if REAL
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 612e25b116..2f1b790bcb 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,7 +24,6 @@
 #include <cbmem.h>
 #include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
-#include <southbridge/intel/common/rcba.h>
 #include "sandybridge.h"
 
 static void sandybridge_setup_bars(void)
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index e81d3bfc55..577296258e 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -59,7 +59,6 @@
 #define IOMMU_BASE2		0xfed91000ULL
 
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/rcba.h>
 
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
-- 
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