From 4d192820cd22b019b916cbaab16f0384c661038d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 12 Dec 2020 13:54:37 +0100 Subject: nb/intel/sandybridge: Add comment to TC_RWP write Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9b364ab92b..a21caeacff 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1885,6 +1885,10 @@ int write_training(ramctr_timing *ctrl) int channel, slotrank; int err; + /* + * Set the DEC_WRD bit, required for the write flyby algorithm. + * Needs to be done before starting the write training procedure. + */ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); -- cgit v1.2.3