From 4a216475f5382d4b0ccf5fb65cd79b7ca3b32ed4 Mon Sep 17 00:00:00 2001
From: Jacob Garber <jgarber1@ualberta.ca>
Date: Fri, 27 Dec 2019 14:18:32 -0700
Subject: src: Remove some romcc workarounds

Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.

Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/northbridge/intel/gm45/bootblock.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'src/northbridge')

diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index dda2b585f1..58b99ac40b 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -14,9 +14,7 @@
 #include <arch/bootblock.h>
 #include <device/pci_ops.h>
 
-/* Just re-define these instead of including gm45.h. It blows up romcc. */
-#define D0F0_PCIEXBAR_LO 0x60
-#define D0F0_PCIEXBAR_HI 0x64
+#include "gm45.h"
 
 void bootblock_early_northbridge_init(void)
 {
-- 
cgit v1.2.3