From 45a0dbc95c1ef1d697598655a526709f27151bb4 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 30 Mar 2017 17:07:42 +0200 Subject: nb/intel: Deduplicate vbt header Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/18903 Tested-by: build bot (Jenkins) Tested-by: coreboot org Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/northbridge/intel/fsp_sandybridge/acpi.c | 1 + src/northbridge/intel/fsp_sandybridge/gma.h | 168 --------------------- .../intel/fsp_sandybridge/northbridge.h | 2 +- src/northbridge/intel/haswell/acpi.c | 1 + src/northbridge/intel/haswell/gma.h | 168 --------------------- src/northbridge/intel/haswell/haswell.h | 2 +- src/northbridge/intel/nehalem/gma.h | 117 -------------- src/northbridge/intel/nehalem/nehalem.h | 2 +- src/northbridge/intel/sandybridge/gma.c | 1 + src/northbridge/intel/sandybridge/gma.h | 97 ------------ src/northbridge/intel/sandybridge/sandybridge.h | 2 +- 11 files changed, 7 insertions(+), 554 deletions(-) delete mode 100644 src/northbridge/intel/fsp_sandybridge/gma.h delete mode 100644 src/northbridge/intel/haswell/gma.h delete mode 100644 src/northbridge/intel/nehalem/gma.h (limited to 'src/northbridge') diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 7744fea5d0..a30cb7a576 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -27,6 +27,7 @@ #include #include "northbridge.h" #include +#include unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h deleted file mode 100644 index 5693e0c66d..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/gma.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Chromium OS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H -#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H - -/* mailbox 0: header */ -typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; - -#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 - -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) - -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) -#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) - -#define SBIOS_VERSION_SIZE 32 - -/* mailbox 1: public acpi methods */ -typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; - -/* mailbox 2: software sci interface */ -typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; - -/* mailbox 3: power conservation */ -typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; - -#define IGD_BACKLIGHT_BRIGHTNESS 0xff -#define IGD_INITIAL_BRIGHTNESS 0x64 - -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) -#define IGD_PFIT_STRETCH 6 - -/* mailbox 4: vbt */ -typedef struct { - u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; - -/* IGD OpRegion */ -typedef struct { - opregion_header_t header; - opregion_mailbox1_t mailbox1; - opregion_mailbox2_t mailbox2; - opregion_mailbox3_t mailbox3; - opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; - -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index a41b2cab6e..0be01ccb62 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -216,7 +216,7 @@ void report_platform_info(void); #endif /* !__SMM__ */ #if !defined(__PRE_RAM__) -#include "gma.h" +#include int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 37101049e3..cb430f927a 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -27,6 +27,7 @@ #include #include #include +#include unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h deleted file mode 100644 index 5adab5718a..0000000000 --- a/src/northbridge/intel/haswell/gma.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Chromium OS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_HASWELL_GMA_H -#define NORTHBRIDGE_INTEL_HASWELL_GMA_H - -/* mailbox 0: header */ -typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; - -#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 - -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) - -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) -#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) - -#define SBIOS_VERSION_SIZE 32 - -/* mailbox 1: public acpi methods */ -typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; - -/* mailbox 2: software sci interface */ -typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; - -/* mailbox 3: power conservation */ -typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; - -#define IGD_BACKLIGHT_BRIGHTNESS 0xff -#define IGD_INITIAL_BRIGHTNESS 0x64 - -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) -#define IGD_PFIT_STRETCH 6 - -/* mailbox 4: vbt */ -typedef struct { - u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; - -/* IGD OpRegion */ -typedef struct { - opregion_header_t header; - opregion_mailbox1_t mailbox1; - opregion_mailbox2_t mailbox2; - opregion_mailbox3_t mailbox3; - opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; - -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -#endif /* NORTHBRIDGE_INTEL_HASWELL_GMA_H */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 6e587f8640..f0fe07d91d 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -214,7 +214,7 @@ void report_platform_info(void); #endif /* !__SMM__ */ #if !defined(__PRE_RAM__) -#include "gma.h" +#include int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h deleted file mode 100644 index 92d6fbef55..0000000000 --- a/src/northbridge/intel/nehalem/gma.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ - -/* mailbox 0: header */ -typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; - -#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 - -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) - -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) -#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) - -#define SBIOS_VERSION_SIZE 32 - -/* mailbox 1: public acpi methods */ -typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; - -/* mailbox 2: software sci interface */ -typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; - -/* mailbox 3: power conservation */ -typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; - -#define IGD_BACKLIGHT_BRIGHTNESS 0xff -#define IGD_INITIAL_BRIGHTNESS 0x64 - -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) -#define IGD_PFIT_STRETCH 6 - -/* mailbox 4: vbt */ -typedef struct { - u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; - -/* IGD OpRegion */ -typedef struct { - opregion_header_t header; - opregion_mailbox1_t mailbox1; - opregion_mailbox2_t mailbox2; - opregion_mailbox3_t mailbox3; - opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; - -#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index bc6bde2d5d..5385b8e695 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -301,7 +301,7 @@ void report_platform_info(void); #endif /* !__SMM__ */ #if !defined(__PRE_RAM__) -#include "gma.h" +#include int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 70216007a8..dcc992c940 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -27,6 +27,7 @@ #include "chip.h" #include "sandybridge.h" +#include "gma.h" struct gt_powermeter { u16 reg; diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 534b42e151..5b10920f7d 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -16,103 +16,6 @@ #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H #define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H -/* mailbox 0: header */ -typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; -} __attribute__((packed)) opregion_header_t; - -#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 - -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) - -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) -#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) - -#define SBIOS_VERSION_SIZE 32 - -/* mailbox 1: public acpi methods */ -typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; -} __attribute__((packed)) opregion_mailbox1_t; - -/* mailbox 2: software sci interface */ -typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; -} __attribute__((packed)) opregion_mailbox2_t; - -/* mailbox 3: power conservation */ -typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; -} __attribute__((packed)) opregion_mailbox3_t; - -#define IGD_BACKLIGHT_BRIGHTNESS 0xff -#define IGD_INITIAL_BRIGHTNESS 0x64 - -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) -#define IGD_PFIT_STRETCH 6 - -/* mailbox 4: vbt */ -typedef struct { - u8 gvd1[7168]; -} __attribute__((packed)) opregion_vbt_t; - -/* IGD OpRegion */ -typedef struct { - opregion_header_t header; - opregion_mailbox1_t mailbox1; - opregion_mailbox2_t mailbox2; - opregion_mailbox3_t mailbox3; - opregion_vbt_t vbt; -} __attribute__((packed)) igd_opregion_t; - struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e737e50f65..8d2ae852e5 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -236,7 +236,7 @@ unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start #endif #if !defined(__PRE_RAM__) -#include "gma.h" +#include int init_igd_opregion(igd_opregion_t *igd_opregion); #endif -- cgit v1.2.3