From 3e1b3b1f4f48cfa3b2af28f44c0537ea19d0e8cb Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sun, 7 Oct 2018 12:45:47 +0200
Subject: sb/amd/cimx/sb[89]00: Use CF9 reset

Implement board_reset() as "system reset".

Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29056
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/amd/agesa/family14/state_machine.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/northbridge')

diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index fd9e3d0eaa..81ce57f13b 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -18,11 +18,11 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <halt.h>
-#include <reset.h>
 #include <smp/node.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -46,7 +46,7 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 		u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
 		if (mct_cfg_lo & (1<<19)) {
 			printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
-			hard_reset();
+			system_reset();
 		}
 	}
 }
-- 
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