From 372dfe0e20f7e56ba2acf872392da41f5ee28633 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 18 Nov 2023 17:47:22 +0100 Subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Patrick Rudolph --- src/northbridge/intel/sandybridge/chipset.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index a08b1bd2cb..83680c12e9 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -37,7 +37,7 @@ chip northbridge/intel/sandybridge device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge - device pci 1f.0 alias lpc on end # LPC bridge + device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 device pci 1f.3 alias smbus on end # SMBus device pci 1f.5 alias sata2 off end # SATA Controller 2 -- cgit v1.2.3