From 3580d816e6d7a08434d91e9e1acdb94a47f07836 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 11 Jun 2020 14:13:33 +0200 Subject: nb/intel/i945: Put names to northbridge PCI devices Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/bootblock.c | 2 +- src/northbridge/intel/i945/early_init.c | 58 ++++++++++++++++----------------- src/northbridge/intel/i945/i945.h | 2 ++ src/northbridge/intel/i945/memmap.c | 10 +++--- src/northbridge/intel/i945/raminit.c | 44 +++++++++++++------------ 5 files changed, 61 insertions(+), 55 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 9a1444365a..9d06120ecb 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -18,5 +18,5 @@ void bootblock_early_northbridge_init(void) * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a8c160a22d..b04a2f5940 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -15,7 +15,7 @@ int i945_silicon_revision(void) { - return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); + return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION); } static void i945m_detect_chipset(void) @@ -23,7 +23,7 @@ static void i945m_detect_chipset(void) u8 reg8; printk(BIOS_INFO, "\n"); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; switch (reg8) { case 1: printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); @@ -46,7 +46,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5; switch (reg8) { case 2: printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ @@ -63,7 +63,7 @@ static void i945m_detect_chipset(void) printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 2: printk(BIOS_DEBUG, "up to DDR2-667"); @@ -89,8 +89,8 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "\nIntel(R) "); - reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) - | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); + reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4) + | ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3); switch (reg8) { case 0: case 1: @@ -116,7 +116,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 0: case 2: @@ -144,10 +144,10 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) @@ -155,25 +155,25 @@ static void i945_setup_bars(void) /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; - pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4)); /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -245,7 +245,7 @@ static void i945_setup_egress_port(void) } /* Is internal graphics enabled? */ - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) MCHBAR32(MMARB1) |= (1 << 17); /* Assign Virtual Channel ID 1 to VC1 */ @@ -405,7 +405,7 @@ static void i945_setup_dmi_rcrb(void) #endif DMIBAR32(0x204) = reg32; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { printk(BIOS_DEBUG, "Internal graphics: enabled\n"); DMIBAR32(0x200) |= (1 << 21); } else { @@ -501,7 +501,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); - pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0); + pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0); pci_and_config32(p2peg, PEGCC, ~(1 << 8)); @@ -600,9 +600,9 @@ static void i945_setup_pci_express_x16(void) if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); + pci_write_config16(HOST_BRIDGE, GGC, reg16); - pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); + pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); } /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ @@ -698,7 +698,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "ok\n"); /* Finally: Disable the PCI config header */ - pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0); + pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0); } static void i945_setup_root_complex_topology(void) @@ -738,7 +738,7 @@ static void i945_setup_root_complex_topology(void) DMIBAR32(DMILE2A) = DEFAULT_EPBAR; /* PCI Express x16 Port Root Topology */ - if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); pci_or_config32(p2peg, LE1D, 1 << 0); } @@ -777,7 +777,7 @@ static void ich7_setup_pci_express(void) void i945_early_initialization(void) { /* Print some chipset specific information */ - switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { + switch (pci_read_config32(HOST_BRIDGE, 0)) { case 0x27708086: /* 82945G/GZ/GC/P/PL */ i945_detect_chipset(); break; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 20558b31cb..5275d1bfb7 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -31,6 +31,7 @@ #define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x44 @@ -88,6 +89,7 @@ /* Device 0:2.0 PCI configuration space (Graphics Device) */ +#define IGD_DEV PCI_DEV(0, 2, 0) #define GMADR 0x18 #define GTTADR 0x1c diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 07aea98d17..c92e4662d6 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -36,20 +36,20 @@ static uintptr_t northbridge_get_tseg_base(void) { uintptr_t tom; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); + tom = pci_read_config32(IGD_DEV, BSM); else - tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; + tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24; /* subtract TSEG size */ - tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); + tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC)); return tom; } static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); return decode_tseg_size(esmramc); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cfe4d8f1c8..2a8a42bedb 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -137,7 +137,7 @@ static int sdram_capabilities_max_supported_memory_frequency(void) return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY; #endif - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 &= (7 << 0); switch (reg32) { @@ -161,7 +161,7 @@ static int sdram_capabilities_interleave(void) { u32 reg32; - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 >>= 25; reg32 &= 1; @@ -177,7 +177,7 @@ static int sdram_capabilities_dual_channel(void) { u32 reg32; - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 >>= 24; reg32 &= 1; @@ -188,7 +188,7 @@ static int sdram_capabilities_enhanced_addressing_xor(void) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ + reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ reg8 &= (1 << 7); return (!reg8); @@ -203,7 +203,7 @@ static int sdram_capabilities_core_frequencies(void) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ + reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ reg8 &= (1 << 3) | (1 << 2) | (1 << 1); reg8 >>= 1; @@ -1186,13 +1186,13 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); - pci_write_config8(PCI_DEV(0, 0, 0), TOLUD, tolud); + pci_write_config8(HOST_BRIDGE, TOLUD, tolud); printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0)); printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0)); - printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0, 0, 0), TOLUD)); + printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(HOST_BRIDGE, TOLUD)); - pci_write_config16(PCI_DEV(0, 0, 0), TOM, tom); + pci_write_config16(HOST_BRIDGE, TOM, tom); return 0; } @@ -1625,7 +1625,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) /* Gate graphics hardware for frequency change */ reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */ - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); /* Get graphics frequency capabilities */ reg8 = sdram_capabilities_core_frequencies(); @@ -1651,7 +1651,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) if (freq != CRCLK_400MHz) { /* What chipset are we? Force 166MHz for GMS */ - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; if (reg8 == 2) freq = CRCLK_166MHz; } @@ -1701,10 +1701,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) sysinfo->clkcfg_bit7 = 0; /* Graphics Core Render Clock */ - pci_update_config16(PCI_DEV(0, 2, 0), GCFC, ~((7 << 0) | (1 << 13)), freq); + pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq); /* Graphics Core Display Clock */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC); + reg8 = pci_read_config8(IGD_DEV, GCFC); reg8 &= ~((1 << 7) | (7 << 4)); if (voltage == VOLTAGE_1_05) { @@ -1714,19 +1714,19 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) reg8 |= CDCLK_320MHz; printk(BIOS_DEBUG, " Display: 320MHz\n"); } - pci_write_config8(PCI_DEV(0, 2, 0), GCFC, reg8); + pci_write_config8(IGD_DEV, GCFC, reg8); - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1); + reg8 = pci_read_config8(IGD_DEV, GCFC + 1); reg8 |= (1 << 3) | (1 << 1); - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); reg8 |= 0x0f; - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); /* Ungate core render and display clocks */ reg8 &= 0xf0; - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); } static void sdram_program_memory_frequency(struct sys_info *sysinfo) @@ -2185,7 +2185,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg16 |= (4 << 11); MCHBAR16(CPCTL) = reg16; +#if 0 + if ((MCHBAR32(ECO) & (1 << 16)) != 0) { +#else if (i945_silicon_revision() != 0) { +#endif switch (sysinfo->fsb_frequency) { case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; @@ -2260,9 +2264,9 @@ static void sdram_power_management(struct sys_info *sysinfo) MCHBAR32(FSBPMC4) |= (1 << 4); } - pci_or_config8(PCI_DEV(0, 0x0, 0), 0xfc, 1 << 4); + pci_or_config8(HOST_BRIDGE, 0xfc, 1 << 4); - pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2); + pci_or_config8(IGD_DEV, 0xc1, 1 << 2); if (integrated_graphics) { MCHBAR16(MIPMC4) = 0x04f8; @@ -2702,7 +2706,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) sdram_program_graphics_frequency(&sysinfo); else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + pci_write_config16(IGD_DEV, GCFC, 0x0534); /* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); -- cgit v1.2.3