From 346d201d73d51ae0a037f64b1bc6d530745b5d4a Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 23 Mar 2019 10:07:16 +0200 Subject: nb/intel/i945: Use DEBUG_RAM_SETUP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 18 ++---------------- src/northbridge/intel/i945/i945.h | 1 + src/northbridge/intel/i945/raminit.c | 2 -- src/northbridge/intel/i945/raminit.h | 4 ---- 4 files changed, 3 insertions(+), 22 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d3ed27745d..08dd6752d6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -940,22 +940,8 @@ void i945_late_initialization(int s3resume) i945_setup_root_complex_topology(); -#if !CONFIG(HAVE_ACPI_RESUME) -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG(DEBUG_RAM_SETUP) - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + sdram_dump_mchbar_registers(); MCHBAR16(SSKPD) = 0xCAFE; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 8c082416bc..ebcc8bcb19 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -375,6 +375,7 @@ void print_pci_devices(void); void dump_pci_device(unsigned int dev); void dump_pci_devices(void); void dump_spd_registers(void); +void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a93cf1e718..05b577787d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -96,7 +96,6 @@ static void ram_read32(u32 offset) read32((void *)offset); } -#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -108,7 +107,6 @@ void sdram_dump_mchbar_registers(void) printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i)); } } -#endif static int memclk(void) { diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d1eee6947..e9e66d13e1 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,8 +69,4 @@ void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); void udelay(u32 us); - -#if CONFIG(DEBUG_RAM_SETUP) -void sdram_dump_mchbar_registers(void); -#endif #endif /* RAMINIT_H */ -- cgit v1.2.3