From 242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 23 Nov 2017 21:23:44 +0100 Subject: intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/i945/udelay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 90f2638251..8447453435 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -56,7 +56,7 @@ void udelay(u32 us) break; } - msr = rdmsr(0x198); + msr = rdmsr(IA32_PERF_STATUS); divisor = (msr.hi >> 8) & 0x1f; d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ -- cgit v1.2.3