From 1cfafe25e37d3a396a19bfe524af16284ff41070 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 7 Jan 2020 12:00:31 +0200 Subject: intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/raminit.c | 3 --- src/northbridge/intel/x4x/romstage.c | 2 -- 2 files changed, 5 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b1da177281..5b8d1d811e 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1723,9 +1723,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) while (!(read8((u8 *)0xfed40000) & (1 << 7))) {} } - /* Enable SMBUS. */ - enable_smbus(); - /* Collect information about DIMMs and find common settings. */ collect_dimm_config(sysinfo); diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index eae87f3674..26d336bfd2 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,8 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; - enable_smbus(); - #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) i82801jx_early_init(); #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -- cgit v1.2.3