From 1c505f82773d345ffdb35d2ad0026f5630ff2d1b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 11 Nov 2020 20:55:35 +0100 Subject: nb/intel/sandybridge: Move IOSAV functions to separate file Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/raminit_common.c | 33 ---------------- src/northbridge/intel/sandybridge/raminit_common.h | 5 +++ src/northbridge/intel/sandybridge/raminit_iosav.c | 46 ++++++++++++++++++++++ 4 files changed, 52 insertions(+), 33 deletions(-) create mode 100644 src/northbridge/intel/sandybridge/raminit_iosav.c (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a5b2e5efb6..63806819de 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,7 @@ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c +romstage-y += raminit_iosav.c romstage-y += raminit_native.c romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 20c048f7f2..ebb9e4488b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,31 +18,6 @@ /* FIXME: no support for 3-channel chipsets */ -/* Number of programmed IOSAV subsequences. */ -static unsigned int ssq_count = 0; - -static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) -{ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; - - ssq_count++; -} - -static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) -{ - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); - - ssq_count = 0; -} - -static void iosav_run_once(const int ch) -{ - iosav_run_queue(ch, 1, 0); -} - static void sfence(void) { asm volatile ("sfence"); @@ -546,14 +521,6 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) } } -static void wait_for_iosav(int channel) -{ - while (1) { - if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) - return; - } -} - static void write_reset(ramctr_timing *ctrl) { int channel, slotrank; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index a6f4e0ba85..73c28bc689 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,11 @@ struct iosav_ssq { } addr_update; }; +void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq); +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); +void iosav_run_once(const int ch); +void wait_for_iosav(int channel); + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c new file mode 100644 index 0000000000..9ab415ab0b --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "raminit_native.h" +#include "raminit_common.h" +#include "raminit_tables.h" +#include "sandybridge.h" + +/* FIXME: no support for 3-channel chipsets */ + +/* Number of programmed IOSAV subsequences. */ +static unsigned int ssq_count = 0; + +void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) +{ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; + + ssq_count++; +} + +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) +{ + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); + + ssq_count = 0; +} + +void iosav_run_once(const int ch) +{ + iosav_run_queue(ch, 1, 0); +} + +void wait_for_iosav(int channel) +{ + while (1) { + if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) + return; + } +} -- cgit v1.2.3