From 154768b902384bc53d30eefa83f89e79eaf4ec2f Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 26 Jul 2013 08:53:59 +0300 Subject: intel PCI ops: Remove explicit PCI MMCONF access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/fsp_sandybridge/finalize.c | 22 +++++++++++----------- src/northbridge/intel/nehalem/finalize.c | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c index 19cfdb7981..4ceb75688e 100644 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ b/src/northbridge/intel/fsp_sandybridge/finalize.c @@ -22,17 +22,17 @@ void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index be4397b369..0b5cb74ce2 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -22,17 +22,17 @@ void intel_nehalem_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ -- cgit v1.2.3