From 1233c43a983f0e05cf19c670b790d5e0fe66e2af Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 29 Jul 2022 07:34:03 +0200 Subject: nb/intel/sandybridge: Align TOUUD down to 1 MiB granularity This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 14fde8b08a..521044bcba 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -85,7 +85,7 @@ static uint64_t get_touud(const struct device *dev) { uint64_t touud = pci_read_config32(dev, TOUUD + 4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= pci_read_config32(dev, TOUUD) & 0xfff00000; return touud; } -- cgit v1.2.3