From 118d105a375618a8ee8309cd9dcdc17ea6d31f30 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 9 Jul 2013 15:34:25 -0700 Subject: haswell: Export functions for CPU family+model and stepping These are needed to enable workarounds/features on specific CPU types and stepping. The older northbridge function and defines from sandybridge/ivybridge are removed. Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/61333 Commit-Queue: Aaron Durbin Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4355 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/intel/haswell/haswell.h | 18 ------------------ src/northbridge/intel/haswell/northbridge.c | 14 -------------- 2 files changed, 32 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 7d451a91da..c9e10ed4f5 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -26,23 +26,6 @@ #define HASWELL_DESKTOP 1 #define HASWELL_SERVER 2 -/* Device ID for SandyBridge and IvyBridge */ -#define BASE_REV_SNB 0x00 -#define BASE_REV_IVB 0x50 -#define BASE_REV_MASK 0x50 - -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ -#define SNB_STEP_D1 (BASE_REV_SNB + 6) -#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 (BASE_REV_IVB + 0) -#define IVB_STEP_B0 (BASE_REV_IVB + 2) -#define IVB_STEP_C0 (BASE_REV_IVB + 4) -#define IVB_STEP_K0 (BASE_REV_IVB + 5) -#define IVB_STEP_D0 (BASE_REV_IVB + 6) - /* Intel Enhanced Debug region */ #define IED_SIZE CONFIG_IED_REGION_SIZE @@ -215,7 +198,6 @@ struct ied_header { #ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); #else /* !__SMM__ */ -int bridge_silicon_revision(void); void haswell_early_initialization(int chipset_type); void haswell_late_initialization(void); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index be1b61456b..bdf87b1616 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,20 +39,6 @@ #include "chip.h" #include "haswell.h" -static int bridge_revision_id = -1; - -int bridge_silicon_revision(void) -{ - if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( - dev_find_slot(0, PCI_DEVFN(0, 0)), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - return bridge_revision_id; -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; -- cgit v1.2.3