From 11739a48ce08d1ef11bfd54670ec23a1ee6daccd Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 18:37:45 -0500 Subject: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue AMD Opteron processors contain a very fragile phy phase detection circuit. Additionally, the algorithm given in the BKDG does not function as intended; this was verified both on real hardware via execution trace and on paper with values read back from multiple CPUs and DIMMs. As a result, the phy training algorithm given in the BKDG has been replaced with a phy training algorithm developed at Raptor Engineering. This particular patch is the first part of that algorithm; the code is updated in future patches but this should exist in the historical record in case something breaks down in the later sections of code. Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12007 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 496803e94b..dfddb60609 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT pDCTData->WLCriticalGrossDelayPrevPass = cgd; + if (pDCTstat->Speed != pDCTstat->TargetFreq) { + /* FIXME + * Using the Pass 1 training values causes major phy training problems on + * all Family 15h processors I tested (Pass 1 values are randomly too high, + * and Pass 2 cannot lock). + * Figure out why this is and fix it, then remove the bypass code below... + */ + if (pass == FirstPass) { + for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; + pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; + } + return 0; + } + } + /* Compensate for occasional noise/instability causing sporadic training failure */ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { uint8_t faulty_value_detected = 0; -- cgit v1.2.3