From 0d2fdeb36afdd3cfd7576b4c2fb79e134bb58630 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 20:29:55 -0500 Subject: amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12037 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4b4a0381a5..d76eea0e2a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5313,6 +5313,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ val |= (0x1 << 8); val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ + val |= (0x1 << 20); /* DblPrefEn = 0x1 */ val |= (0x7 << 22); /* PrefFourConf = 0x7 */ val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ -- cgit v1.2.3