From 03b00e9675d08d01ff831f20e8e48d19e93494af Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Tue, 20 May 2014 15:52:08 -0700 Subject: baytrail: Fix some minor errors in FSP - Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses. (thanks for Mike Hibbett for pointing this out) Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/5798 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index f7bb023b59..0537c54769 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -89,7 +89,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data);/home/martin/extra/git/coreboot + GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); ConfigureDefaultUpdData(fsp_upd_data); #else pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; -- cgit v1.2.3